1. Field of the Invention
Example embodiments of the present invention relate in general to a semiconductor memory device, and more particularly to a signal input stage of a semiconductor memory device, and a multi-chip package that utilizes the semiconductor memory device having the signal input stage.
2. Description of the Related Art
With the development of semiconductor technologies, functions and capacity of a single chip have increased as more elements have been integrated into the same chip area. Also, in an aspect of a packaging technology of a semiconductor chip, technologies corresponding to leaner and lighter products have been developed while the functions and the capacity of the single chip have been developed. Such technologies, including a multi-chip package (MCP) technology and a multi-stack package (MSP) technology, which can mount a plurality of semiconductor chips in a single semiconductor package, have been widely used.
The multi-chip package technology is a technology that constitutes one package by enabling a plurality of semiconductor chips to be mounted onto one lead frame. The multi-chip package technology is frequently applied to an application field such as a portable device necessarily requiring the leaner and lighter product. For instance, the multi-chip package technology is widely used for various purposes that realize a high capacity of memory by stacking multiple memory chips, and integrate various kinds of memory chips and controllers into one package.
One type of multi-chip package is a dual die package (DDP) in which two chips are mounted in one package. Although there exists a method for arraying two chips in parallel in one dual die package, a method for minimizing the size of the package area by stacking two chips is more widely used.
FIG. 1 is a cross-sectional view illustrating a conventional dual die package having a stacked structure.
Referring to FIG. 1, in the dual die package 100, a first semiconductor chip 110 and a second semiconductor chip 120 are attached onto upper and lower surfaces of a die pad 130, respectively. A pad 111 of the first semiconductor chip 110 and a pad 121 of the second semiconductor chip 120 are electrically connected to upper and lower surfaces of an inner end of a lead 140, respectively, via a wire-bonding using conductive metal wires 141 and 142. The inner end of the lead 140 is spaced apart from the die pad 130 by a predetermined interval.
Further, elements including the first and second semiconductor chips 110 and 120 are protected from the external environment by a package body 150 formed with plastic materials such as epoxy molding resin.
In this case, bottom surfaces, on which a pad is not formed, of the first and second semiconductor chips 110 and 120 are attached onto the upper and the lower surfaces of the die pad 130. A non-conductive bonding agent made of epoxy or a bonding tape made of polyimide (PI) materials have been used as bonding agents 151 and 152.
There may be two types of dual die packages. In a first type of dual die package, one chip is stacked over another chip. In a second type of dual die package, two chips are arranged in parallel.
As illustrated in FIG. 1, irrespective of the two types of dual die packages, it is necessary to divide the two chips existing in the package.
For instance, in a case of the first type of dual die package, it is necessary to identify a top chip (TOP) located in a top portion and a bottom chip (BOTTOM) located in a bottom portion. Conventionally, in addition to a chip select signal or a clock enable pad existing in respective chips, there exist other pads for determining whether a corresponding chip is located in the top or the bottom portion, thereby allowing the top chip (TOP) and the bottom chip (BOTTOM) to be identified according to a bonding state of the pads.
Further, recently, a chip select pin or a clock enable pin in a dual die package has been prepared for the top chip (TOP) and the bottom chip (BOTTOM). The chip select pin or the clock enable pin is connected respectively to a chip select pad or a clock enable pad of each of the chips. For instance, in a case of the first type of dual die package in which two memory chips are stacked, a chip select pin (CSB0) for the top chip (TOP) and a chip select pin (CSB1) for the bottom chip (BOTTOM) are prepared in the package. The chip select pin (CSB0) is connected to the chip select pad of the top chip (TOP), and the chip select pin (CSB1) is connected to the chip select pad of the bottom chip (BOTTOM), respectively.
However, there may be a case where the positions of the chip select pins (CSB0) and (CSB1) in the dual die package are arranged differently from each other, or a case where a wiring routing from a pad of a semiconductor chip to a pin of a package can be difficult depending upon a mounted direction of a semiconductor chip. Accordingly, a method has been used for increasing the degree of freedom for package construction by providing two or more chip select pads or clock enable pads in one semiconductor chip. The two or more chip select pads or clock enable pads in one semiconductor chip perform a common function, and either two or more chip select pads or clock enable pads can be bonded to pins of the dual die package. However, in this case, the other pads that are not bonded to the pins of the package are in a not-connected state (NC), i.e., a floating state. When the other pads are continuously left in the floating state, a current due to an uncertain level of the other pads in the floating state may be induced to other circuits connected to the other pads. In order to prevent the induced current, the level of the pads that are not bonded needs to be internally fixed. However, it is difficult to recognize which pad is not bonded among two or more pads.
FIG. 2 is a block diagram illustrating an input stage of a conventional semiconductor device.
Referring to FIG. 2, an input stage of a conventional semiconductor device 200 includes at least two pads including a first pad 201 and a second pad 202, an electrical conductor 203 for electrically connecting the at least two pads, and an input buffer 204 for receiving an output signal outputted from the two pads 201, 202.
As illustrated in FIG. 2, the input stage of the semiconductor device 200 has a common electrical potential by connecting two or more pads to the electrical conductor.
For instance, when the first pad 201 is bonded to a chip select pin of an external package and the second pad 202 is in a floating state, the same input signal may be inputted to an internal circuit through the input buffer 204 because the first and second pads 201 and 202 have the same signal potential due to the electric conductor 203. Likewise, the operation is similar even in a case in which the second pad 202 is bonded to the chip select pin of the external package and the first pad 201 is in the floating state.
However, in the case of the input stage of the semiconductor device as illustrated in FIG. 2, there is a drawback in that the first and second pads 201 and 202 have increased input capacitances and increased clamp characteristics in comparison with the other pads since the two pads 201, 202 are connected through the electric conductor 203.